As non-volatile semiconductor memory devices, an EEPROM (electrically erasable and programmable read only memory), a flash memory and the like are known. These non-volatile semiconductor memory devices are utilized as recording media of various products such as digital still cameras, portable audio players and cellular phones. Research and development of the non-volatile semiconductor memory devices have been actively conducted to meet the needs of the market, for example, further reduction in the size of the product, increase in memory capacity, increase in the speed of writing and reading data, and reduction in power consumption.
As one of the ways to meet the aforementioned needs of the market, in recent years, a non-volatile semiconductor memory device of a so-called SOI (silicon on insulator) type has been actively developed, in which elements are formed on a silicon film that is provided over a substrate with an insulating film interposed therebetween.
For example, Patent Document 1 discloses a non-volatile memory transistor having an SOI structure, which has been made to reduce cost and the operating voltage such as an erasing voltage. In Patent Document 1, a glass substrate or a plastic substrate is used as a substrate to reduce cost. A non-volatile memory transistor having an SOI structure, which is formed over a glass substrate, is disclosed in, for example, Patent Document 2 that is a patent application of which one of the inventors is the inventor of the present invention.    [Patent Document 1] Japanese Published Patent Application No. 2006-013534    [Patent Document 2] Japanese Published Patent Application No. 2007-288176
In the non-volatile memory elements having an SOI structure as disclosed in Patent Documents 1 and 2, however, it is very difficult to reduce a writing voltage and an erasing voltage without increasing the area of a memory cell. The reason for that will be explained below. Here, the case of using a non-volatile memory transistor (hereinafter, also abbreviated to a memory transistor) as a non-volatile memory element will be made described. First, the structure of a memory cell will be described and then, the method for writing, reading and erasing data will be described.
The structure of a memory cell will be described below with reference to FIG. 15 and FIGS. 16A and 16B. FIG. 15 is a plan view illustrating an example of a structure of a conventional memory cell, and FIGS. 16A and 16B are cross-sectional views taken along lines A1-A2 and B1-B2 of FIG. 15, respectively.
In the memory cell, one memory transistor is provided as a memory element, and the memory transistor is electrically connected to a source line (SL), a bit line (BL) and a word line (WL).
As illustrated in FIGS. 16A and 16B, an insulating film 1130 is formed over a substrate 1100, and an island-shaped semiconductor region 1102 is provided over the insulating film 1130. The island-shaped semiconductor region 1102 includes first impurity regions 1103 and 1104 doped with an n-type or p-type impurity element, second impurity regions 1105 and 1106 doped with an n-type or p-type impurity element, and a channel formation region 1107 interposed between the second impurity regions 1105 and 1106. The second impurity regions 1105 and 1106 may be formed as LDD (lightly doped drain) regions having an impurity concentration lower than that of the first impurity regions 1103 and 1104; may have an impurity concentration substantially equal to that of the first impurity regions 1103 and 1104; or may have an impurity concentration substantially equal to that of the channel formation region 1107 without being doped with an impurity element. The second impurity regions 1105 and 1106 may be formed in accordance with the characteristics of the memory element.
An insulating film 1108 is provided over the island-shaped semiconductor region 1102. A conductive film 1109 is provided over the insulating film 1108 so as to overlap the island-shaped semiconductor film 1102. The conductive film 1109 forms a floating gate (FG) of the memory transistor. An insulating film 1110 is provided over the conductive film 1109. A conductive film 1111 is provided over the insulating film 1110 so as to overlap the island-shaped semiconductor region 1102. The conductive film 1111 forms a control gate (CG) of the memory transistor and the word line electrically connected to the control gate. By forming both the control gate and the word line using the conductive film 1111, the control gate and the word line are electrically connected to each other.
An insulating film 1112 is provided over the conductive film 1111, and conductive films 1113 and 1114 are formed over the insulating film 1112. The conductive film 1113 forms a source line (SL) electrically connected to the memory transistor, and the conductive film 1114 forms a bit line (BL) electrically connected to the memory transistor. Through openings 1119 and 1120 formed in the insulating film 1112, the conductive films 1113 and 1114 are electrically connected to the first impurity regions 1103 and 1104, respectively. A region 1121 surrounded by an alternate long and two short dashes line of FIG. 15 is a region occupied by one memory cell.
The non-volatile memory transistor using a floating gate is a memory element in which data is stored in accordance with the amount of charge accumulated in the floating gate. Data is written or erased by controlling the amount of charge, and data is read by detecting the amount of charge. The method for writing, reading and erasing data will be described below.
In the memory transistor of FIG. 15, the floating gate (the conductive film 1109) is in an electrically floating state. Accordingly, the memory transistor functions as a transistor when a voltage is indirectly applied between the island-shaped semiconductor region 1102 and the floating gate from the control gate (the conductive film 1111). When electrons are accumulated in the floating gate, the voltage that has been applied to the control gate is less likely to be applied between the island-shaped semiconductor region 1102 and the floating gate than that when electrons are not accumulated; therefore, the threshold voltage of the memory transistor shifts to the positive direction. Thus, the data stored in the memory transistor can be read by detecting a change in the threshold voltage of the memory transistor. If the first impurity region 1103 and the first impurity region 1104 have the same potential, the relationship between the amount of charge accumulated in the floating gate and the threshold voltage can be represented by the following formulas (1) and (2).
                              V          FG                =                                            C              2                                                      C                1                            +                              C                2                                              ⁢                      (                                          V                CG                            -                              Δ                ⁢                                                                  ⁢                Vtm                                      )                                              (        1        )                                          Δ          ⁢                                          ⁢          Vtm                =                  -                                    Q              FG                                      C              2                                                          (        2        )            
In the formulas (1) and (2), VFG is the potential of the floating gate; VCG, the potential of the control gate; C1, the capacitance between the island-shaped semiconductor region and the floating gate; C2, the capacitance between the floating gate and the control gate; QFG, the amount of charge in the floating gate; and ΔVtm, a change in the threshold voltage of the memory transistor. Note that C2/(C1+C2) in the formula (1) is generally referred to as a coupling ratio. As shown in the formula (1), as the coupling ratio increases, the ratio of the voltage applied between the island-shaped semiconductor region 1102 and the floating gate to the potential VCG of the control gate increases.
When data is to be written to the memory transistor, a high voltage (e.g., a positive high voltage) is applied to the control gate so that a voltage is indirectly applied between the island-shaped semiconductor region 1102 and the floating gate. Then, electrons are injected into the floating gate by an F-N (Fowler-Nordheim) tunneling current or thermal electrons. When data is to be erased from the memory transistor, a high voltage (e.g., a negative high voltage) is applied to the control gate so that a voltage is indirectly applied between the island-shaped semiconductor region 1102 and the floating gates whereby electrons are withdrawn from the floating gate.
Thus, the voltage applied to the control gate can be efficiently applied between the island-shaped semiconductor region 1102 and the floating gate by increasing the coupling ratio, so that a writing voltage and an erasing voltage can be reduced. In other words, the coupling ratio significantly influences the writing voltage and the erasing voltage.
The relationship between the area of the memory cell and the writing and erasing voltages as well as the relationship between the area of the memory cell and the coupling ratio will be described below.
As shown in the formula (1), in order to increase the coupling ratio, it is effective to increase the capacitance C2 between the floating gate and the control gate. The capacitance C2 can be increased by either reducing the thickness of the insulating film 1110 or increasing the area where the floating gate and the control gate overlap each other in the plan view (layout) of FIG. 15.
However, the minimum thickness of the insulating film 1110 is automatically decided based on the aforementioned operating principle of the memory transistor, and there is a limitation on reduction in the thickness of the insulating film 1110. This is because it is difficult for the memory transistor using a floating gate to retain the stored data if the charge accumulated in the floating gate is easily leaked. Thus, the thickness of the insulating film 1110 cannot be smaller than a predetermined thickness. For a similar reason, the thickness of the insulating film 1108 cannot be smaller than a predetermined thickness. The thickness of the insulating film 1108 is preferably about 8 nm to 10 nm, and the thickness of the insulating film 1110 is preferably about 10 nm to 20 nm.
Since the insulating film 1110 is provided over the floating gate while the insulating film 1108 is provided over the island-shaped semiconductor region 1102, the insulating film 1110 is less reliable as an insulating film than the insulating film 1108. Accordingly, it is generally said that the thickness of the insulating film 1110 needs to be larger than that of the insulating film 1108 to prevent the leakage of charge from the floating gate. In addition, in the case where the insulating film 1110 is too thin when the coupling ratio is low, electrons to be accumulated in the floating gate tunnel through the insulating film 1110 and escape to the control gate in writing. Accordingly, data cannot be written or erased, which may cause improper function as a memory element. Furthermore, in the case where functional circuits other than the memory cell are formed over the same substrate 1100, the thickness of the insulating film 1110 cannot be sufficiently reduced in some cases depending on the manufacturing process of transistors forming the functional circuits.
Thus, increasing the area of a region where the floating gate and the control gate overlap in the plan view of FIG. 15 is an easy method to increase the coupling ratio because the operation of the memory transistor is not particularly damaged. However, increasing this area is disadvantageous in that the area of the memory cell required for the memory element increases to reduce the integration of memory cells, leading to a higher bit cost of the non-volatile semiconductor memory device.
Furthermore, when the area of the memory cell is reduced in the plan view of FIG. 15, the area where the floating gate and the control gate overlap each other is also reduced, which leads to a lower coupling ratio and higher writing and erasing voltages.